Computing with switching lattices consisting of four-terminal switches was first proposed in [1]. Since then there have been many studies in the literature focusing on the optimization of the size of switching lattices, in terms of the number of four terminal switches, to implement a given Boolean function [2-8]. However, the literature lacks concrete justifications for device realization of switching lattices. In this invention, we develop a CMOS-technology-compatible device for a four-terminal switch, and show the formation of a lattice using this device.    [1] M. Altun and M. Riedel, “Lattice-based computation of Boolean functions,” in Proceedings of the 47th Design Automation Conference (DAC), 2010.    [2] M. Altun and M. Riedel, “Logic synthesis for switching lattices,” IEEE Transactions on Computers, vol. 61, pp. 1588-1600, 2012.    [3] G. Gange, H. Søndergaard, and P. J. Stuckey, “Synthesizing optimal switching lattices,” ACM TODAES, vol. 20, pp. 6:1-6:14, 2014.    [4] A. Bernasconi, V. Ciriani, L. Frontini, V. Liberali, G. Trucco, and T. Villa, “Logic synthesis for switching lattices by decomposition with p-circuits,” in DSD, 2016, pp. 423-430.    [5] A. Bernasconi, V. Ciriani, L. Frontini, and G. Trucco, “Synthesis of switching lattices of dimensional-reducible boolean functions,” in VLSI-SoC, 2016, pp. 1-6. A.    [6] Bernasconi, V. Ciriani, L. Frontini, and G. Trucco, “Composition of switching lattices for regular and for decomposed functions,” MICPRO, vol. 60, pp. 207-218, 2018.    [7] M. Morgul and M. Altun, “Optimal and heuristic algorithms to synthesize lattices of four-terminal switches,” Integration, in press.    [8] L. Aksoy and M. Altun, “A satisfiability-based approximate algorithm for logic synthesis using switching lattices,” to be in the proceedings of Design, Automation, and Test in Europe (DATE), 2019.
The dominant technology in electronic device technology is the CMOS technology. Today, the most widely used devices are based on a two-terminal switching architecture. Two-terminal switches are realized with MOSFET devices comprising gate, source, drain and bulk terminals. The gate is located over the channel between source and drain. When voltage is applied between the gate and the bulk, gate and majority carriers are collected in the channel resulting in current flow between drain and source terminals. Concentration of collected carriers controls magnitude of the electric current. These devices act as two-terminal switches controlled by the gate. While no current flows between source and drain in the two-terminal switches which are off, a significant current can flow between source and drain in two-terminal switches which are on. Logic functions are implemented by turning switches on or off. This technology continues to be used as the mainstay of modern electronic computers and related technologies. We develop a CMOS-technology-compatible device for a four-terminal switch, and show the formation of a lattice using this device.
The U.S. Pat. No. 7,365,377 refers to a four-terminal transistor based lattice-shaped structure; here, a back gate bias is applied to a four-terminal transistor in an LSI. The deep N-well region, all of the N-well regions and the P-well regions are placed in the same structure. The back gates of the N-channel MOS transistors and all of the P-channel MOS transistors on the chip are interconnected. In the related document, the functionality of the interconnections is highlighted and it is mentioned that there will be restrictions on the dimensions of the device due to required connections.
The U.S. Pat. No. 4,638,344 refers to a system which can be integrated into real three-dimensional circuits and all other known devices having connections that are made of the same conductivity type material. Therefore, metal contacts, electrodes, or interconnections are not required to form the system. As there is no need for metal interconnections and insulation regions the system has been made more suitable to create more concentrated forms of logic than known systems. In the relevant document, it is possible to operate with the control of the channel placement. Switching is carried out by two-terminals.
The U.S. Pat. No. 8,633,547B2 refers to a physical system layout of a semiconductor system comprising MOSFETs (metal oxide semiconductor field effect transistors) formed on a semiconductor substrate. The development of this physical settlement minimizes the use of time and resource. Here, a metal lattice structure in which metal layers, N-well regions, and deep N-well regions are positioned under one surface of the semiconductor device.
The U.S. Pat. No. 9,847,334 refers to a semiconductor system having high dimensional capability, feature size (the smallest component that can be created using a manufacturing process), functional density (number of interconnected devices for each chip die). This system provides benefits by increasing production efficiency and reducing related costs.
Although, the above mentioned patents are related to a CMOS or a CMOS-compatible device or technology, and some of them mention lattice structures. None of these patents is about switching lattices consisting of four-terminal switches. Therefore, there is no direct connection of these patents with the invention.